Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 195

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parallel Input/Output
OVERVIEW
FEATURES
UM008101-0601
The Z80 Parallel Input/Output (PIO) Circuit is a programmable, two-port
device that provides a TTL-compatible interface between peripheral
devices and the Z80 CPU. The CPU configures the Z80 PIO to interface
with a wide range of peripheral devices with no other external logic
required. Typical peripheral devices that are fully compatible with the Z80
PIO include most keyboards, paper tape readers and punches, printers, and
PROM programmers. The Z80 PIO package is available in 40-pin DIP, 44-
pin PLCC, or 44-pin QFP. The CMOS version is available in all three pack-
age configurations. The NMOS version is available in 40-pin DIP and 44-
pin PLCC.
One unique feature that separates the Z80 PIO from other interface control-
lers is that all data transfers between the peripheral device and the CPU is
under total interrupt control. The PIO interrupt logic allows full use of the
efficient interrupt capabilities of the Z80 CPU during I/O transfers. All
logic necessary to implement a fully nested interrupt structure is included in
the PIO, requiring no additional circuits. Another unique feature is that the
PIO can be programmed to interrupt the CPU on the occurrence of speci-
fied status conditions in the peripheral device. For example, the PIO can be
programmed to interrupt when any specified peripheral alarm conditions
occur. This interrupt capability reduces the amount of time spent by the pro-
cessor polling peripheral status.
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Two independent 8-Bit bidirectional peripheral interface ports with
handshake data transfer control
Interrupt-driven handshake for fast response
<   % 2 7 2 G T K R J G T C N U
Parallel Input/Output
7 U G T / C P W C N