Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 203

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
3. Bidirectional mode: When this signal is active, data from the Port A
4. Control mode: The strobe is inhibited internally.
ARDY
Register A Ready (output, active High). The meaning of this signal depends
on the mode of operation selected for Port A as follows:
1. Output mode: This signal goes active to indicate that the Port A
2. Input mode: This signal is active when the Port A input register is
3. Bidirectional mode: This signal is active when data is available in the
4. Control mode: This signal is disabled and forced to a Low state.
B7-B0
Port B Bus (bidirectional, tristate). This 8-bit bus is used to transfer data
and/or status or control information between Port B of the PIO and a
peripheral device. The Port B data bus is capable of supplying 1.5 mA @
1.5V to drive Darlington transistors. B0 is the least significant bit of the bus.
BSTB
Port B Strobe Pulse from Peripheral Device (input, active Low). The
meaning of this signal is similar to that of ASTB with the following
exception: In the Port A bidirectional mode, this signal strobes data from
the peripheral device into the Port A input register.
output register is gated onto Port A bidirectional data bus. The
positive edge of the strobe acknowledges the receipt of the data.
output register has been loaded and the peripheral data bus is stable
and ready for transfer to the peripheral device.
empty and is ready to accept data from the peripheral device.
Port A output register for transfer to the peripheral device. In this
mode, data is not placed on the Port A data bus unless ASTB is active.
<   % 2 7 2 G T K R J G T C N U
Parallel Input/Output
7 U G T / C P W C N