Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 308

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

288
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Request To Send (D1)
This is the control bit for The RTS pin. When the RTS bit is set, the RTS
pin goes Low; when reset, RTS goes High. In the Asynchronous mode,
RTS goes High only after all the bits of the character are transmitted and
the transmitter buffer is empty. In Synchronous modes, the pin directly
follows the state of the bit.
CRC-16/SDLC (D2)
This bit selects the CRC polynomial used by both the transmitter and
receiver. When set, the CRC-16 polynomial (X
when reset, the SDLC polynomial (X
mode is selected, the CRC generator and checker are preset to 1s and a
special check sequence is used. The SDLC CRC polynomial must be
selected when the SDLC mode is selected. If the SDLC mode is not selected,
the CRC generator and checker are preset to 0s for both polynomials.
Transmit Enable (D3)
Data is not transmitted until this bit is set, and the Transmit Data output is
held marking. Data or sync characters in the process of being transmitted
are completely sent if this bit is reset after transmission is started. If the
transmitter is disabled during the transmission of a CRC character, sync, or
flag characters are sent instead of CRC.
Send Break (D4)
When set, this bit immediately forces the Transmit Data output to the
spacing condition, regardless of any data being transmitted. When reset,
TxD returns to marking.
16
+ X
12
+ X
16
+X
5
+ 1) is used. If the SDLC
15
+ X
Serial Input/Output
2
+ 1) is used;