Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 217

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERRUPT SERVICING
UM008101-0601
After an interrupt is requested by the PIO, the CPU sends out an interrupt
acknowledge (M1 and IORQ). During this time, the interrupt logic of the
PIO determines which port has the highest priority interrupt. (This is a
device which has an Interrupt Enable Input High and an Interrupt Enable
Output Low). To insure that the daisy-chain enable lines stabilize, devices
are inhibited from changing their interrupt request status when M1 is
active. The highest priority device places the contents of its interrupt
vector register onto the Z80 data bus during interrupt acknowledge.
Figure 11 illustrates the timing associated with interrupt requests. During
M1 time, no new interrupt requests can be generated. This allows time for
the lnt Enable signals to ripple through up to four PIO circuits. The PIO,
with IEI High and IEO Low during INTA, places the 8-bit interrupt
vector of the appropriate port on the data bus at this time.
If an interrupt requested by the PIO is acknowledged, the requesting port
is under service. The IEO of this port remains low until a return from
interrupt instruction (RETI) is executed, during which time the IEI of the
port is High. If an interrupt request is not acknowledged, IEO is forced
High for one M1 cycle after the PIO decodes the Op Code ED. This
action guarantees that the 2-byte RETI instruction is decoded by the
correct PIO port (Figure 12).
Figure 13 illustrates a typical nested interrupt sequence that could occur
with four ports connected in the daisy-chain. In this sequence, Port 2A
requests and is granted an interrupt. While this port is being serviced, a
higher priority port (1B) requests and is granted an interrupt. The service
routine for the higher priority port is completed and a RETI instruction is
executed, indicating to the port that its routine is complete. The service
routine of the lower priority port is then complete.
<   % 2 7 2 G T K R J G T C N U
Parallel Input/Output
7 U G T / C P W C N