Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 25

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3. Interrupt Vector Register
UM008101-0601
Bit Number
7–3
2–1
0
7
Interrupt Control Logic
6
Field
Reserved
Channel Identifier
(Automatically
inserted by CTC)
Word
The Interrupt Control Logic insures that the CTC acts in accordance with
Z80 system interrupt protocol for Nested Priority Interrupting and Return
From Interrupt. The priority of any system device is determined by its
physical location in a daisy-chain configuration. Two signal lines, CIEI and
IEO, are provided in CTC devices to form this system daisy-chain. The
device closest to the CPU has the highest priority. Within the CTC,
interrupt priority is predetermined by channel number, with Channel 0
having highest and Channel 3 the lowest priority. See Table 3. The purpose
of a CTC-generated interrupt, as with any peripheral device, is to force the
CPU to execute an interrupt service routine. According to Z80 system
interrupt protocol, lower priority devices or channels may not interrupt
higher priority devices or channels that have not had their interrupt service
routines completed. However, high priority devices or channels may
interrupt the servicing of lower priority devices or channels.
Supplied by User
5
R/W
4
R/W
R/W
R/W
R/W
Value Description
11
10
01
00
1
0
3
Supplied by User
Channel 3
Channel 2
Channel 1
Channel 0
Control
Interrupt Vector
2
Channel Identifier
Counter/Timer Channels
R/W
<   % 2 7 2 G T K R J G T C N U
1
7 U G T / C P W C N
0
Word
R/W