Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 279

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
259
the Z80 SIO with this mode using the Wait/Ready function. The Z80 SIO
transmits the Frame Check sequence using the Transmit Underrun feature.
SDLC Transmit Underrun/End of Message
SDLC-like protocols do not have provisions for fill characters within a
message. The Z80 SIO therefore automatically terminates an SDLC frame
when the transmit data buffer and output shift register have no more bits to
send. It does this by first sending the two bytes of CRC followed by one or
more flags. This technique allows very high-speed transmissions under
DMA or CPU block I/O control without requiring the CPU to respond
quickly to the end of message condition.
The Z80 SIO response to the underrun condition depends on the state of the
Transmit Underrun/EOM command. Following a reset, the Transmit
Underrun/EOM status bit is in the set state and prevents the insertion of
CRC characters while there is no data to send. Consequently, flag charac-
ters are sent. The Z80 SIO starts sending the frame while data is written to
the transmit buffer. Between the time the first data byte is written and the
end of the message, the Reset Transmit Underrun/EOM Command must be
issued. Thus the Transmit Underrun/EOM status bit is in the reset state at
the end of the message (when underrun occurs), which automatically sends
the CRC characters. The sending of CRC again sets the Transmit/Underrun/
EOM status bit.
Although there is no restriction about when the Transmit Underrun/EOM
bit can be reset within a message, the reset usually occurs after the first data
character (secondary address) is sent to the Z80 SIO. Resetting this bit
allows CRC and flags to be sent when there is no data to send, allowing
additional time for the CPU to recognize the fault and respond with an abort
command. By resetting this bit early in the message, the entire message is
allotted the maximum amount of CPU response time in an unintentional
transmit underrun situation.
When the External/Status interrupt is set and while CRC is sent, the
Transmit Underrun/EOM bit is set and the Transmit Buffer Empty bit is
reset to indicate that the transmit register is full of CRC data. When CRC
UM008101-0601
Serial Input/Output