Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 34

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CTC OPERATING MODES
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Overview
CTC COUNTER Mode
At power-on, the Z80 CTC state is undefined. Asserting RESET puts the
CTC in a known state. Before a channel can begin counting or timing, a
channel control word and a time constant data word must be written to the
appropriate registers of that channel. Additionally, if a channel has been
programmed to enable interrupts, an interrupt vector word must be written
to the CTC’s interrupt control logic. (For further details, refer the “CTC
Programming” on page 18) When the CPU has written all of these words to
the CTC, all active channels are programmed for immediate operation in
either the COUNTER mode or the TIMER mode.
In CTC COUNTER mode, the CTC counts edges of the CLK/TRG input.
This mode is programmed for a channel when its Channel Control Word is
written with bit 6 set. The channel’s external clock (CLK/TRG) input is
monitored for a series of triggering edges. After each, in synchronization
with the next rising edge of Φ (the System clock), the down-counter (which
is initialized with the Time Constant Data word at the start of each sequence
of down-counting) is decremented. Although there is no setup time
requirement between the triggering edge of the External clock and the
rising edge of Φ (Clock), the down-counter is not decremented until the
following pulse. A channel’s External clock input is pre programmed by bit
4 of the channel control word to trigger the decrementing sequence with
either a high- or a low-going edge.
In Channels 0, 1, or 2, when the down-counter is successively decremented
from the original time constant (until it reaches zero), the Zero Count (ZC/
TO) output pin for that channel is pulsed active (High). Due to package pin
limitations, this pin does not exist on Channel 3 and so this pin may only be
Counter/Timer Channels