Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 78

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Auto Restart
Pulse Generation
Variable Cycle
Block transfers can be repeated automatically by the DMA. This function
causes the byte counter to be cleared and the address counters to be
reloaded with the contents of the starting-address registers.
The Auto Restart feature relieves the CPU of software overhead for repet-
itive operations such as CRT refresh and many others. Moreover, the CPU
can write different starting addresses into the buffer registers during
transfers in the Byte mode (or Burst mode when the Ready line is inactive
and the bus is released) causing the Auto Restart to begin at a new location.
External devices can keep track of how many bytes have been transferred
by using the DMA’s Pulse output, which provides a signal at 256-byte
intervals. The interval sequence may be offset at the beginning by 1 to
255 bytes.
The interrupt line carries the Pulse signal in a manner that prevents inter-
pretation by the Z80 CPU as an interrupt request, because the signal only
appears when the Bus Request and Bus Acknowledge lines are both
active. Under these conditions, the Z80 CPU does not monitor the
Interrupt (INT) line.
The Z80 DMA offers the unique feature of programmable operation-cycle
length. This is valuable in tailoring the DMA to the particular requirements
of various CPUs and other system components (fast or slow), and in maxi-
mizing the data-transfer rate. Also, it often eliminates external logic and
reduces CPU software overhead.
There are two aspects to the variable cycle feature. First, the entire read and
write cycles (periods) associated with the source and destination ports can
Direct Memory Access