Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 316

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Clear To Send, (D5). This bit is similar to the DCD bit, except that it shows
the inverted state of the CTS pin.
Transmit Underrun/End of Message (D6)
This bit is in a set condition following a reset, either internal or external.
The only the Reset Transmit Underrun/EOM Latch command (WR0, D6
and D7) can reset this bit. When the Transmit Underrun condition occurs,
this bit is set; causing the External/Status interrupt, which is reset by issuing
the Reset External/Status Interrupt command bits (WR0). This status bit,
along with other control bits, has an important function in controlling a
transmit operation. For more information, see “Bisync Transmit Underrun”
and “SDLC Transmit Underrun”.
Break/Abort (D7)
In the Asynchronous Receive mode, this bit is set when a Break sequence
(null character plus framing error) is detected in the data stream. The
External/Status interrupt, if enabled, is set when Break is detected. The
interrupt service routine must issue the Reset External/Status Interrupt
command (WR0, CMD2) to the break detection logic, enabling the Break
sequence termination to be recognized.
The Break/Abort bit is reset when the termination of the Break sequence is
detected in the incoming data stream. The termination of the Break
sequence also causes the External/Status interrupt to set. The Reset
External/Status Interrupt command must be issued to enable the break
detection logic to look for the next Break sequence. When a single extra-
neous null character is present in the receiver after the termination of a
break; it should be read and discarded.
In the SDLC Receive mode, this status bit is set by the detection of an
Abort sequence (seven or more 1s). The External/Status interrupt is handled
the same way as a Break. The Break/Abort bit is not used in the Synchro-
nous Receive mode.
Serial Input/Output