Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 58

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Modes of Operation
Within each of the methods illustrated in Figure 16c and Figure 16d there
are up to three modes of operation. These are termed Byte, Burst, and
Continuous modes in this manual, although they are also sometimes
referred to as Single, Demand, and Block modes. Figure 17 illustrates the
typical sequence of events for each mode, when the I/O device’s Ready
signal to the DMAC becomes active and before the DMA process reaches
an end-of-block or other terminating condition. (These figures are
expanded in Figure 20 through Figure 23.)
In Byte mode, the DMAC transfers only one byte at a time while the I/O
device Ready line is active. Control of the system bus is released back to
the CPU between each byte. The CPU can then interleave its other activ-
ities, until the DMA makes a new request to the CPU for system bus control
before transferring the next byte. Byte mode is related to the transparent
method of transfer in that both cause interleaving of CPU and DMA func-
tions. The Byte mode, however, includes the protocol of requesting and
releasing the bus for each byte transfer.
In Burst mode, which is the most common mode, the DMAC continues to
transfer bytes after gaining control of the system bus until the I/O device
Ready line goes inactive. During this time, the CPU typically remains idle.
When the Ready line goes inactive, the DMAC releases system bus control
back to the CPU.
In Continuous mode, the DMAC holds the system bus until the entire block
of data has been transferred. If the I/O device Ready line goes inactive
before the block is completely transferred, the DMAC waits until it
becomes active again, but the system bus is not released as in Burst mode.
The Continuous mode is the fastest mode because it has the least response-
time overhead when the Ready line momentarily goes inactive and returns
active again. However, this mode does not allow any CPU activity for the
duration of the transfer.
Direct Memory Access