Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 97

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
 
Bus Request Daisy-Chains
Multiple DMAs can be linked in a prioritized daisy-chain for the purpose of
requesting the bus. Figure 31 illustrates this procedure.
Each DMA’s BUSREQ pin is bidirectional. As an output, it requests the
bus. As an input, this pin senses when another DMA in the daisy-chain has
requested the bus (brought the BUSREQ line Low) and therefore prevents
this DMA from also requesting the bus until the other DMA has finished.
Any DMA that has the bus is always allowed to finish its operation; a
higher priority DMA cannot preempt it during this time.
Their proximity to the CPU determines the priority of DMAs in a daisy-
chain. The DMA electrically closest to the CPU (as measured along the
BUSACKI/BAI lines) has the highest priority. Priority matters only when
multiple DMAs request the bus on the same clock cycle. The higher
priority DMA can then prevent lower priority DMAs from receiving a bus-
acknowledge signal through the BAI/BAO chain. The lower priority DMAs
continue to hold their BUSREQ lines Low until the higher priority DMA
finishes and releases the bus, thereby allowing lower priority DMAs to
contend for the bus.
1.8K
BUSREQ
CPU
BUSACK
BAI
BUSREQ
BAO
BAI
BUSREQ
BAO
DMA
DMA
Figure 31.
Bus-Requesting Daisy-Chain
UM008101-0601
Direct Memory Access