Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 156

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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signals. To maximize current, the system’s BUSREQ pull-up resistor can be
as low as 1.8 Kohms.
TTL buffers and drive capacitive loads
While the DC output ratings of standard buffers such as the 74LS367 are
usually ample, propagation times through these buffers are rated at capac-
itive loadings of only 30 pF, a value easily exceeded in practice. Capacitive
loading thus usually dominates bus driving requirements. Z80 Family parts
are specified over ranges of capacitive loading.
The load seen by a device driving a bus line has components due to wiring
and printed circuit land capacitance, connector capacitance, and capaci-
tances of inputs and outputs connected to the signal. A standard low-power
Schottky (LS) TTL input presents about 6 pF of capacitive load, an LS
output of about 8 pF. Most other input and output capacitances can be esti-
mated from device data sheets, but capacitance associated with intercon-
nection may vary markedly. Sometimes, propagation delays and allowable
capacitive loading for buffered lines must be determined by measurement
or by trial and error.
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