Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 289

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10. SDLC Receive Mode (Continued)
UM008101-0601
Function
WR4
WR0
WR5
WR0
WR3
WR0
WR6
WR0
WR7
WR0
WR1
WR0
WR3
Typical Program Steps
Parity information, Sync Mode, SDLC
Mode, X1 Clock Mode
Pointer 5, Reset External/Status
Interrupts
SDLC-CRC, Data Terminal Ready
Pointer 3
Receive CRC Enable, enter Hunt Mode,
Auto Enables, Receive Character Length,
Address Search Mode
Pointer 6
Secondary Address Field
Pointer 7
SDLC Flag 0111 1110
Pointer 1, Reset External/Status
Interrupts
Status Affects Vector, External Interrupt
Enable, Receive Interrupt on first
character only.
Pointer 3, Enable Interrupt on next
Receive Character
Receive Enable, Receive CRC Enable,
enter Hunt Mode, Auto Enables,
Receiver Character Length, Address
Search Mode
Comments
Auto Enables enables the receiver to
accept data only after MB becomes
active. Address Search Mode Enables
SIO to match the message address
with the programmed address or the
global address.
This address is compared to the
message address in an SDLC Poll
operation.
This flag detects the start and end-of-
frame in an SDLC Operation. In this
Interrupt Mode, only the address field
(1 character only) is transferred to the
CPU. All subsequent fields (control,
information, and more.) are
transferred on a DMA basis. Status
Affects Vector in Channel B only.
This flag provides simple loop-back
entry point for next transaction.
WR3 reissued to enable receiver.
Z80 CPU Peripherals
Serial Input/Output
User Manual
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