Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 43

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
CTC Read Cycle
CS0. CS1, CE
Note:
Figure 9.
Figure 10 illustrates the timing associated with the CTC Read cycle. This
sequence is used when CPU reads the current contents of the down counter.
During clock cycle T2, the Z80 CPU initiates the Read cycle with true
signals at input pins RD (Read), IORQ (I/O Request), and CE (Chip
Enable). A 2-bit binary code appears at CTC inputs CS1 and CS0 (Channel
Select 1 and 0), specifying which of the four CTC channels is being read
from. (See Note below.) On the rising edge of the cycle T3, the valid
contents of the down-counter rising edge of cycle T2 is available on the
Z80 data bus. No additional wait states are allowed.
IORQ
RD
M1
M1 must be false to distinguish the cycle from an interrupt
acknowledge.
CTC Write Cycle
T
1
T
2
Channel Address
T
WA
T
3
Counter/Timer Channels
<   % 2 7 2 G T K R J G T C N U
T
1
7 U G T / C P W C N