Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 176

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
it Read During
the Last Data
DMA Drives
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
CE/WAIT
this Time
MEMRD
A15–A0
D7–D0
IOWR
CLK
Figure 64.
Figure 63 illustrates the timing for simultaneous transfers in Burst and Con-
tinuous modes between memory and I/O, using standard Z80 timing. The
timing within each cycle is similar to the memory read cycle shown in
Figure 61. The address bus activity is the same, and the cycle length is the
same. However, the MREQ, RD, IORQ, and WR lines in Figure 61 have
been changed to MEMRD and IOWR lines in Figure 63. In addition, the
data bus becomes active earlier in Figure 63, in response to the MEMRD
line becoming active. Data is clocked to the l/O port on the rising edge of
IOWR
Figure 64 depicts the timing for Byte mode. Timing is identical to
Figure 63 within each cycle. The breaks between each cycle, where the
address and data bus are tristated and the MEMRD and IOWR lines remain
Cycle 1
Simultaneous Memory-to-I/O Transfer (Byte Mode)
Cycle 2
Direct Memory Access