Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 141

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
5.
6.
7.
Interrupts at end-of-block, for example, might occur when reading a
floppy disk. If the disk transfers 128-byte records, the DMA can be made
to interrupt at the end of each record to notify the CPU of its completion.
Then the CPU can read the destination (memory) address counter to find
the last memory location filled. See Table 12 for address-counter
contents. A service routine for continuing inputs to contiguous locations
of memory typically contains the
BYTE
interrupt. A service routine for shutting down the DMA after the record
arrives typically includes
BYTE
another device, the service routine for that other device includes an
ENABLE DMA
Interrupts on byte match (a search or transfer/search operation) can be
implemented so that any ending byte, error indicator, or other character
causes the interrupt. This procedure frees the CPU from looking for these
characters in a stream of data, increases throughput, and reduces CPU
software complexity. For example, the DMA might search for end-of-text
(EXT) characters or carriage returns in a communications environment and
interrupt the CPU only when the complete message frame has arrived. The
service routines for this would be very much like those for interrupts on
end-of-block.
Interrupts on Ready are somewhat different. First, the DMA cannot be the
bus master before the interrupt because the CPU only senses interrupts
when the CPU is the bus master (the other types of interrupts are not
•
•
•
ENABLE AFTER RETI
ENABLE DMA
RETI
, and
commands. If the DMA transfer is started by an interrupt from
instruction
ENABLE DMA
command written to the DMA’s port address.
command
commands before the CPU’s return from
DISABLE DMA
command
CONTINUE
and
,
REINITIALIZE STATUS
REINITIALIZE STATUS
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N