Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 315

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
295
When the SYNC input goes High again, another External/ Status interrupt
is generated that must also be cleared. The Enter Hunt Mode control bit is
set whenever character synchronization is lost or the end of message is
detected. In this case, the Z80 SIO again looks for a High-to-Low transition
of the SYNC input and the operation repeats as explained previously. This
implies the CPU should also inform the external logic that character
synchronization has been lost and that the Z80 SIO is wailing for SYNC to
become active.
In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is
initially set to 1 by the Enter Hunt Mode bit. The Sync/Hunt bit is reset
when the Z80 SIO establishes character synchronization. The High-to-Low
transition of the Sync/Hunt bit causes an External/Status interrupt that must
be cleared by the CPU issuing the Reset External/ Status Interrupt
command. This enables the Z80 SIO to detect the next transition of other
External/Status bits.
When the CPU detects the end of message or loss of character synchroniza-
tion, it sets the Enter Hunt Mode control bit, which-in turn-sets the Sync/
Hunt bit to 1. The Low-to-High transition of the Sync/Hunt fit sets the
External/Status interrupt, which must also be cleared by the Reset External/
Status Interrupt command.
The SYNC pin functions as an output in this mode and goes Low when a
sync pattern is detected in the data stream.
In the SDLC mode, the Sync/Hunt bit is initially set by the Enter Hunt
mode bit, or when the receiver is disabled. It is reset to 0 when the opening
flag of the first frame is detected by the Z80 SIO. The External/Status inter-
rupt is also generated, and should be handled as discussed previously.
Unlike the Monosync and Bisync modes, when the Sync/Hunt bit is reset in
the SDLC mode, it does not need to be set when the end of message is
detected. The Z80 SIO automatically maintains synchronization. The Sync/
Hunt bit can only be set again by the Enter Hunt Mode bit or by disabling
the receiver.
UM008101-0601
Serial Input/Output