Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 213
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
Z0847006PSG
Manufacturer:
Zilog
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22
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< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
If the PIO is not in a reset state, the output register may be loaded before
Mode 0 is selected. This allows the port output lines to become active in a
user-defined state.
Φ
WR*
Port Output
(8 Bits)
Ready
Strobe
INT
WR* = RD • CE • C/D • IORQ
Figure 7.
Mode 0 (Output) Timing
Input Mode (Mode 1)
Figure 8 illustrates the timing of an input cycle. The peripheral initiates this
cycle using the strobe line after the CPU has performed a data read. A low
level on this line loads data to the port input register and the rising edge of
the strobe line activates the interrupt request line (INT) if the interrupt
enable is set and this is the highest priority requesting device. The next
falling edge of the clock line (Φ) resets the Ready line to an inactive state,
signifying that the input register is full and further loading must be inhibited
until the CPU reads the data. The CPU, in the course of its interrupt service
routine, reads the data from the interrupting port. When this occurs, the
positive edge from the CPU RD signal raises the Ready line with the next
low going transition of Φ, indicating that new data can be loaded to the
UM008101-0601
Parallel Input/Output
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