Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 145

IC 6MHZ Z80 NMOS DART 40-DIP

Z0847006PSG

Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet

Specifications of Z0847006PSG

Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
Table 16. Sample DMA Program
UM008101-0601
WR0 sets DMA to
receive block length,
Port A starting
address, and
temporarily sets Port
B as source.
Port A address
(lower)
Port A address
(upper)
Block length (lower)
Block length (upper)
WR1 defines Port A
as memory with
fixed incrementing
address
WR4 defines Port A
as memory with
fixed incrementing
address
completed before the next
SEQUENCE
Table 16 illustrates a program to transfer data from memory (Port A) to a
peripheral device (Port B). In this example, the Port A memory starting
address is
number of data bytes to be transferred is
ified by the block length). The table of DMA commands may be stored in
consecutive memory locations and transferred to the DMA with an output
instruction such as the Z80 CPU’s OTIR instruction.
D7
0
0
0
0
0
0
0
Follows
Follows
Follows
Timing
Timing
Length
Upper
Block
1050H
No
No
command.
1
1
0
0
0
0
0
Address
Address
Follows
Change
Length
and the Port B peripheral fixed address is
Upper
Block
Fixed
D5
1
0
0
0
0
0
1
s
Address
Follows
Address
Change
READ STATUS BYTE
Port A
Upper
D4
1
1
1
0
1
1
0
s
Address
Follows
Memor
Port A
Upper
Port is
Port is
I/O
D3
1
0
0
0
0
0
y
1
1001H
Leading
Address
Tempor
ary for
B→A
D2
B
0
0
0
0
0
1
0
or
bytes (one more than spec-
<   % 2 7 2 G T K R J G T C N U
INITIATE READ
Direct Memory Access
Transfer. No
D1
0
0
0
0
0
1
Search
0
7 U G T / C P W C N
05H
D0
0
0
0
0
0
0
. The
HEX
50
10
00
10
14
28
  

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