Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 314

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

294
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
this bit and sets the External/Status interrupt. When the External/Status
interrupt is set by the change in state of any other input or condition, this bit
shows the inverted state of the SYNC pin at the time of the change. This bit
must be read immediately following a Reset External/Status Interrupt
command to read the current state of tile SYNC input.
Figure 122. Read Register 0
In the External Sync mode, the Sync/Hunt bit operates similar to the Asyn-
chronous mode, except the Enter Hunt Mode control bit enables the
external sync detection logic. When the External Sync Mode and Enter
Hunt Mode bits are set for example, when the receiver is enabled following
a reset, the SYNC input must be held High by the external logic until
external character synchronization is achieved. A High at the SYNC input
holds the Sync/Hunt status bit in the reset condition.
When external synchronization is achieved, SYNC must be driven Low on
the second rising edge of RxC after that rising edge of RxC on which the
last bit of the sync character was received. In other words, after the sync
pattern is detected, the external logic must wait for two full Receive Clock
cycles to activate the SYNC input. When SYNC is forced Low, keep it Low
until the CPU informs the external sync logic that synchronization is lost or
that a new message is about to start. Refer to Figure 122 for timing details.
The High-to-Low transition of the SYNC input sets the Sync/Hunt bit,
which, in turn, sets the External/Status interrupt. The CPU must clear the
interrupt by issuing the Reset External/Status Interrupt command.
D7
D6
D5
D4
D3
D2
D1
*Used with ‘External/Status Interrupt Mode
D0
Rx Character Available
INT Pending (CH.A Only
Tx Buffer Empty
DCD
SYNC/Hunt
CTS
Tx Underrun/EOM
Break/Abort
Serial Input/Output
*