Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 125

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
  
cates that it is never loaded. This special situation is discussed in a later
section entitled “Fixed-Address Destination Ports.”
If the DMA is in an inactive state (Table 15) when the LOAD command is
written, another DMA control byte must precede the LOAD. Any other
command, such as DISABLE DMA, serves this purpose. Because LOAD
unforces a Forced-Ready condition, the LOAD must precede a FORCE
READY command when the latter is used.
Continue (D3)
This command clears the byte counter to zero but leaves the address
counters of both ports with their current contents. Transfers or searches
continue from where they left off after an ENABLE DMA command,
although the byte count starts over.
The CONTINUE command is typically used to transfer several blocks to
consecutive locations in memory when it is desirable to know when each
block has finished transferring. Specifically, an interrupt at the end of each
block may be needed. Use this command rather than a LOAD command to
transfer the next block after the interrupt. A new block length can be
entered in WR0 in conjunction with the CONTINUE command.
If the DMA is in an inactive state (Figure 15) when the CONTINUE
command is written, another DMA control byte must precede the
CONTINUE. Any other command, such as DISABLE DMA, serves this
purpose.
Disable Interrupts (AF)
The command is used in non-Z80 CPU environments to simulate the Z80
CPU’s automatic interrupt acknowledge to the DMA. When the DMA
interrupts a non-Z80 CPU, the CPU writes a DISABLE INTERRUPTS to
the DMA early in the service routine. This allows the INT line to go
inactive but prevents the DMA from sending subsequent interrupts while
UM008101-0601
Direct Memory Access