Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 11

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

List of Figures
Direct Memory Access (continued)
Figure 50. CE/WAIT Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Figure 51. Simultaneous Transfer Multiplexer . . . . . . . . . . . . . . . . .133
Figure 52. Simultaneous Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Figure 53. Delaying the Leading Edge of MWR . . . . . . . . . . . . . . . .135
Figure 54. Data Bus Buffer Control Example . . . . . . . . . . . . . . . . . .138
Figure 55. DMA-SIO Environment . . . . . . . . . . . . . . . . . . . . . . . . . .142
Figure 56. Connecting DMA to Demultiplexed Address/Data Buses 145
Figure 57. Z8000/Z80 Peripheral Interface . . . . . . . . . . . . . . . . . . . .147
Figure 58. DMA Bus-Master Gate (Byte or Burst Modes Only) . . . .149
Figure 59. CPU-to-DMA Write Cycle Requirements . . . . . . . . . . . .151
Figure 60. CPU-to-DMA Read Cycle Requirements . . . . . . . . . . . . .152
Figure 61. Sequential Memory-to-I/O Transfer, Standard Timing
Figure 62. Sequential I/O-to-Memory Transfer, Standard Timing
Figure 63. Simultaneous Memory-to-I/O Transfer (Burst and Continuous
Figure 64. Simultaneous Memory-to-I/O Transfer (Byte Mode) . . . .157
Figure 65. Bus Request and Acceptance Timing . . . . . . . . . . . . . . . .159
Figure 66. Bus Release in Byte Mode . . . . . . . . . . . . . . . . . . . . . . . .160
Figure 67. Bus Release on End-of-Block (Burst and
Figure 68. Bus Release on Match (Burst and Continuous Modes) . .161
Figure 69. Bus Release on Not Ready (Burst Mode) . . . . . . . . . . . . .162
Figure 70. RDY Line in Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . .163
Figure 71. RDY Line in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . .164
Figure 72. RDY Line in Continuous Mode . . . . . . . . . . . . . . . . . . . .165
Figure 73. Variable-Cycle and Edge Timing . . . . . . . . . . . . . . . . . . .166
(Searching is Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . .154
(Searching is Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Continuous Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Z80 CPU Peripherals
User Manual
UM008101-0601
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