Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 134

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Bit 0
LOAD command. 1 indicates yes, 0 indicates no.
Bit 1
that is defined as active by bit 3 of WR5. 1 indicates an active Ready line. 0
indicates an inactive Ready line.
Bit 2
Bit 3
that an interrupt is pending (the DMA has its INT line active if the interrupt
has not been acknowledged). A 1 indicates no interrupt pending.
Bit 4
REINITIALIZE STATUS BYTE command. A1 indicates no match was
found. See Table 11 to determine where the match occurred.
Bit 5
RESET, LOAD, CONTINUE, or REINITIALIZE STATUS BYTE
command. A 1 indicates no end-of-block was reached. See Table 12 to
determine the contents of counters when the DMA stops.
Bit 6
Bit 7
Indicates whether the DMA has requested the bus after the fast
Indicates whether the DMA’s RDY pin currently has a signal input
Undefined.
Indicates the state of the Interrupt Pending (IP) latch. A 0 indicates
A 0 indicates that a match has been found after the last RESET or
A 0 indicates that an end-of-block was reached after the last
Undefined.
Undefined.
Direct Memory Access