Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 300

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

280
UM008101-0601
READY is High
READY is High when transmit buffer is full
WAIT
READY is Low when transmit buffer is empty
WAIT
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
is low when transmit buffer is full and
S10 data port is an selected
is floating when transmit buffer is empty WAIT
data. The Wait function is selected by setting D6 to 0. If this bit is 0, the
WAIT/READY output is in the open-drain state and goes Low when active.
Both the Wait and Ready functions can be used in either the Transmit or
Receive modes, but not both simultaneously. If D5 (Wait/Ready on Receive/
Transmit) is set to 1, the Wait/Ready function responds to the condition of
the receive buffer (empty or full). If D5 is set to 0, the Wait/Ready function
responds to the condition of the transmit buffer (empty or full).
The logic states of the WAIT/READY output, which are either active or
inactive, depend on the combination of modes selected. Table 18 summa-
rizes these combinations.
Table 18. Wait/Ready Functions
The WAIT output High-to-Low transition occurs at the delay time
tDIC(WR) after the I/O request. The Low-to-High transition occurs at the
delay tDHΦ(WR) at the falling edge of Φ. The READY output High-to-
Low transition occurs at the delay tDLΦ(WR) at the rising edge of Φ. The
READY output Low-to-High transition occurs at the delay tDIC(WR)
after IORQ falls.
The Ready function can occur when the Z80 SIO is not selected. When
the READY output becomes active Low, the DMA controller issues
and D6 = 1
and D5 = 0
If D7 = 0
If D7 = 0
WAIT
READY is High when receive buffer is empty
WAIT
READY is Low when receive buffer is full
and SID data port is selected
is floating
is Low when receive buffer is empty
is floating when receive buffer is full
and D6 = 0
and D5 = 1
Serial Input/Output