Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 143

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
  
End-of-Block
After a stop or stop and interrupt on end-of-block (WR4 or WR5), where it
is necessary to perform additional operations with the DMA, write the same
sequence of commands listed immediately under “Byte Matching
(Searches)” on page 124. Table 12 on page 76 describes the contents of
various counters when stopping on end-of-block.
Auto Restart
To obtain a repetitive transfer or search using the same block length and
starting addresses originally entered, initialize the DMA including WR%
bit 5 = 1. Loading of addresses and clearing of the byte counter is auto-
matic.
When in Byte mode (or Burst mode where the Ready line is occasionally
released), it is possible to alter the starting addresses during a transfer (for
example, between bus requests) without disturbing that transfer. At the end
of this transfer, the DMA automatically loads the new addresses to the
counter and continues without interruption.
Force Ready Condition
The
command is provided for operations such as memory-to-
FORCE READY
memory transfer or memory search-only where no Ready line from an I/O
device is used. However, several DMA commands unforce the Ready
condition after the
command is written. The sequence of
FORCE READY
command entry is therefore important. This sequence is described in the
command in “Write Register 6 Group” on page 105.
FORCE READY
Pulse Generation
To obtain pulses at 256-byte intervals, after a variable offset period,
consider only the WR4 group. The INT line is used for these pulses.
UM008101-0601
Direct Memory Access