Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 287

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
267
Special Receive Condition Interrupts
The Special Receive Condition interrupt is not, as such, a separate interrupt
mode. Before the Special Receive condition can cause an interrupt, either
Interrupt On First Receive Character only or Interrupt On Every Character
must be selected. The Special Receive Condition interrupt is caused by a
Receive Overrun or End-of-Frame detection. When the Receive Overrun
status bit is latched, the error status read indicates that an error occurred in
the current word in the receive buffer in addition to any errors received after
the last Error Reset command. The Receive overrun status bit can only be
reset by the Error Reset command. The End-of-Frame status bit indicates
that a valid ending flag has been received and that the CRC Error and
Residue codes are also valid.
Character length may be changed on-the-fly. If the address and control
bytes are processed as 8-bit characters, the receiver may be switched to a
shorter character length while the first information character is being
assembled. This change must be made fast enough so that it is effective
before the number of bits specified for the character length have been
assembled. For example, if the change is to be from the 8-bit control field to
a 7-bit information field, the change must be made before the first seven
bits of the I-Field are assembled.
SDLC Receive CRC Checking
Control of the receive CRC checker is automatic. It is reset by the leading
flag and CRC is calculated up to the final flag. The byte that has the End-of-
Frame bit set is the byte that contains the result of the CRC check. If the
CRC/Framing Error bit is not set, the CRC indicates a valid message. A
special check sequence is used for the SDLC check because the transmitted
CRC check is inverted. The final check must be
.
0001 1101 0000 1111
The 2-byte CRC check characters must be read by the CPU and discarded
because the Z80 SIO, while using them for CRC checking, treats them as
ordinary data.
UM008101-0601
Serial Input/Output