Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 283

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. SDLC Transmit Mode (Continued)
UM008101-0601
Function
Idle Mode
WR4
WR0
WR1
WR0
WR5
WR0
Typical Program Steps
Parity Information, SDLC
Mode, X1 Clock Mode
Pointer 1. Reset External/Status
Interrupts
External Interrupt Enable,
Status Affects Vector, Transmit
Interrupt Enable or Wait/Ready
Mode Enable
Pointer 5
Transmit CRC Enable, Request
to Send, SDLC-CRC Transmit
Enable, Transmit Word Length,
Data Terminal Ready
Reset Transmit CRC Generator Initialize CRC Generator to all 1s
Execute Halt Instruction or
some other program
Comments
The External Interrupt Mode monitors the
status of the CTS and DCD inputs, as well as
the status of Tx Underrun/EOM Latch.
Transmit Interrupt interrupts when the transmit
butter becomes empty; the Wait/Ready mode
can be used to transfer data on a DMA or block
transfer basis. The first Interrupt occurs when
CTS becomes active, at which time flags are
transmitted by the Z80 SIO. The first data byte
(address field) can be loaded in the Z80 SIO
after this interrupt. Flags cannot be sent to the
Z80 SIO as data. Status Affects Vector used in
Channel B only.
SDLC-CRC Mode must be defined before
initializing Transmit CRC Generator
Waiting for Interrupt or Wait/Ready output to
transfer data
Z80 CPU Peripherals
Serial Input/Output
User Manual
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