Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 24

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant


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the down-counter counts to zero, the down-counter is automatically
reloaded with the contents of the Time Constant register. This process
divides the System clock by an additional factor of the time constant. Each
time the down-counter counts to zero, its output, Zero Count/Timeout (ZC/
TO), is pulsed High.
The Time Constant Register
The 8-bit Time Constant register is used in both Counter and Timer modes.
It is programmed by the CPU just after the channel control word, with an
integer time constant value of 1 through 256. This register loads the
programmed value to the down-counter when the CTC is first initialized
and reloads the same value into the down-counter automatically whenever
it counts down thereafter to zero. If a new time constant is loaded into the
Time Constant register while a channel is counting or timing, the present
down count is completed before the new time constant is loaded into the
down counter. For details about writing a time constant to a CTC channel,
see “CTC Programming” on page 18
The Down-Counter
The down-counter is an 8-bit register that is used in both COUNTER and
TIMER modes. This register is loaded by the Time Constant register both
initially, and when it counts down to zero. In the COUNTER mode, the
down-counter is decremented by each external clock edge. In the TIMER
mode, it is decremented by the clock output of the prescaler. By performing
a simple I/O Read at the port address assigned to the selected CTC channel,
the CPU can access the contents of the down-counter and obtain the number
of counts-to-zero. Any of the four CTC channels may be programmed to
generate an interrupt request sequence each time the zero count is reached.
In Channels 0, 1, and 2, a signal pulse appears at the corresponding ZC/TO
pin when the zero count condition is reached. Because of package pin
limitations, however, Channel 3 does not have this pin and so may be used
only in applications where this output pulse is not required.
Counter/Timer Channels