Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 199

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
  
The interrupt control logic section handles all CPU interrupt protocol for
nested priority interrupt structures. The priority of any device is determined
by its physical location in a daisy-chain configuration. Two lines are
provided in each PIO to form this daisy-chain. The device closest to the
CPU has the highest priority. Within a PIO, Port A interrupts have higher
priority than those of Port B. In the byte input, byte output or bidirectional
modes, an interrupt can be generated whenever a new byte transfer is
requested by the peripheral. In the bit control mode an interrupt can be
generated when the peripheral status matches a programmed value. The
PIO provides for complete control of nested interrupts. That is, lower
priority devices may not interrupt higher priority devices that have not had
their interrupt service routine completed by the CPU. Higher priority
devices may interrupt the servicing of lower priority devices.
When an interrupt is accepted by the CPU in Mode 2, the interrupting
device must provide an 8-bit interrupt vector for the CPU. This vector is
used to form a pointer to a location in the computer memory where the
address of the interrupt service routine is located. The 8-bit vector from the
interrupting device forms the least-significant eight bits of the indirect
pointer while the I Register in the CPU provides the most-significant eight
bits of the pointer. Each port (A and B) has an independent interrupt vector.
The least-significant bit of the vector is automatically set to a 0 within the
PIO because the pointer must point to two adjacent memory locations for a
complete 16-bit address.
The PIO decodes the RETI (Return from interrupt) instruction directly from
the CPU data bus so that each PIO in the system knows at all times whether
it is being serviced by the CPU interrupt service routine without any other
communication with the CPU.
UM008101-0601
Parallel Input/Output