Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 169

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING
UM008101-0601
The CPU As Bus Master
System throughput is decreased for applications requiring frequent DMA
reprogramming or extensive interrupt service of data-independent DMA
functions. It is more efficient to transfer large blocks of repetitive data.
When the CPU is the bus master, control bytes can program the Direct
Memory Access (DMA).
Writing Control Bytes
Table 13 illustrates the disabled, enabled/inactive, or enabled/stopped
states. The enabled/inactive and enabled/stopped states are equivalent. The
DMA is programmed by being addressed as an I/O peripheral in a CPU
output instruction. The DMA can be addressed in the full 64K I/O space. To
accomplish this, three lines must be simultaneously active-Low on the ris-
ing edge of the clock:
Figure 59 illustrates the timing required for this process. In a Z80 CPU
environment, this timing occurs automatically when the CPU and DMA are
on the same board and have no buffers, drivers, or other external gates in
series with the common CPU and DMA pins. This timing applies to the
sequential transfer, sequential transfer/search, and search-only classes of
operation. It may or may not apply to the simultaneous transfer or simulta-
neous transfer/search operations, depending on the speed of the external
devices used (see the Applications chapter).
IORQ Input/Output Request
WR Write
CE Chip Enable
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N