Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 298

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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UM008101-0601
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detection and termination, or at the beginning of CRC or sync character
transmission when the Transmit Underrun/EOM latch sets.
Transmitter Interrupt Enable (D1)
If enabled, interrupts occur whenever the transmitter buffer becomes empty.
Status Affects Vector (D2)
This bit is active in Channel B only. If this bit is not set, the fixed vector
programmed in WR2 is returned from an interrupt acknowledge sequence.
If this bit is set, the vector returned from an interrupt acknowledge is
variable. Table 16 describes the vector results.
Receive Interrupt modes.
Table 16. Vector Results
Receive Interrupt Modes 0 and 1 (D3 and D4)
Used together, these two bits specify the various character-available condi-
tions. In Receive Interrupt modes 1, 2, and 3, a Special Receive Condition
can cause an interrupt that modifies the interrupt vector.
Ch B
Ch A
Note: *Special Receive Conditions: Parity Error, Rx Overrun Error, Framing Error, End-
of-Frame (SDLC).
V3
0
0
0
0
1
1
1
1
V2
0
0
1
1
0
0
1
1
V1
0
1
0
1
0
1
0
1
Ch B Transmit Buffer Empty
Ch B External/Status Change
Ch B Receive Character Available
Ch B Special Receive Condition*
Ch A Transmit Buffer Empty
Ch A External/Status Change
Ch A Receive Character Available
Ch A Special Receive Condition*
Result
Table 17
Serial Input/Output
describes the