Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 290

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

270
Table 10. SDLC Receive Mode (Continued)
UM008101-0601
Function
Idle Mode
Data Transfer and
Status
Monitoring
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Typical Program Steps
Execute Halt Instruction or some other
program
When Interrupt On First Character
occurs, the CPU
performs the following:
• Transfers Data Byte (address byte) to
CPU
• Detects And Sets appropriate Flag for
Extended Address Field
• Updates pointers and parameters
• Enables DMA Controller
• Enables Wait/Ready function in SIO
• Returns from Interrupt
When the Ready Output becomes active,
the DMA Controller performs the
following:
• Transfers the Data Byte to memory
• Updates the pointers
Comments
SDLC Receive Mode is fully
initialized and SIO is waiting for the
opening flag followed by a matching
address field to interrupt the CPU.
During the Hunt Phase, the SIO
interrupts when the programmed
address matches the message address.
The CPU establishes the DMA Mode
and all subsequent data characters are
transferred by the DMA controller to
memory.
During the DMA operation, the SIO
monitors the DCD Input and the Abort
sequence in the data stream to
interrupt the CPU with external status
error. The special receive condition
interrupt is caused by the Receive
Overrun Error.
Serial Input/Output