Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 83

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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7 U G T / C P W C N
 
be preempted by higher priority devices before the lower priority device
has been fully serviced.
INT/PULSE
Interrupt Request (output, active Low, open-drain). This requests a CPU
interrupt when brought Low while the DMA is not the bus master. The
CPU acknowledges the interrupt by pulling its IORQ output Low during an
M1 cycle. The DMA INT pin is typically connected to the INT pin of the
CPU with a pull-up resistor and tied to all other INT pins in the system.
This pin can also be used to generate periodic pulses to an external device.
It can be used this way only when the DMA is bus master, for example, the
CPU’s BUSREQ and BUSACK lines are both Low and the CPU cannot
sense interrupts.
IORQ
Input/Output Request (bidirectional, active Low, tristate). Used as an input,
this pin indicates that the lower half of the address bus contains a valid I/O
port address for transfer of control or status bytes from or to the CPU. This
DMA is the addressed port if its CE pin, IORQ pin, and or RD pin are
simultaneously active. As an output, after the DMA has taken control of the
system buses, this pin indicates that the address bus contains a valid 8-bit or
16-bit port address for another I/O device involved in a DMA transfer of
data. When IORQ and M1 are both active inputs to the DMA, an interrupt
acknowledge by the CPU is indicated.
M1
Machine Cycle One (input, active Low). This pin indicates that the current
CPU machine cycle is an instruction fetch. This pin has two purposes in the
DMA’s interrupt structure. First, it is used by the DMA to detect return-
from-interrupt instructions (RETI, or ED4DH) fetched over the data bus by
the CPU at the end of interrupt service routines. Second, an interrupt
acknowledge is indicated when both M1 and IORQ are active inputs to the
DMA. During 2-byte instruction fetches, M1 is active as each Op Code
byte is fetched. In the CMOS DMA, the M1 signal has a different function:
UM008101-0601
Direct Memory Access