Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 42

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CTC TIMING
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Overview
CTC Write Cycle
Note:
This section describes the timing relationships of the relevant CTC pins for
the following types of operation:
•
•
•
A timing diagram, Figure 12, relating to interrupt servicing is found in
“Interrupt Acknowledge Cycle” on page 28.
Figure 9 illustrates the timing associated with the CTC Write cycle. This
sequence is applicable to loading a channel control word, an interrupt
vector, or a time constant data word.
In the sequence shown, during clock cycle T1, the Z80 CPU prepares for
the Write cycle with a false (High) signal at CTC input pin RD (Read).
Because the CTC has no separate Write signal input, it generates its own
input internally from the false RD input. During clock cycle T2, the Z80
CPU initiates the Write cycle with true (Low) signals at CTC input pins
IORQ (I/O Request) and CE (Chip Enable). (See Note below.) A 2-bit
binary code appears at CTC inputs CS1 and CS0 (Channel Select 1 and 0),
specifying which of the four CTC channels is being written to. At this time,
a channel control, interrupt vector, or time constant data word may be
loaded to the appropriate CTC internal register in synchronization with the
rising edge beginning clock cycle T3.
Writing a word to the CTC
Reading a word from the CTC
Counting and timing
M1 must be false to distinguish the cycle from an interrupt
acknowledge.
Counter/Timer Channels