Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 144

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Variable Timing
The timing on the RD, WR, MREQ, and IORQ lines can be varied indepen-
dently for either port by programming the WR1 and/or WR2 register groups.
When programming memory-to-I/O, I/O-to-memory, or I/O-to-I/O
sequential transfers or transfer/searches, the IORQ line must be programmed
in a specific way. See “Variable Cycle (Port A)” on page 96.
Enabling the DMA
The last command written to the DMA before an operation occurs must be
the
this command makes the DMA operate. If all other conditions for operation
are satisfied at the time of enabling (for example, the Ready line is active)
the DMA begins immediately. In an interrupt service routine, the
DMA
from-interrupt instruction. Other instructions usually follow the
DMA
executed, but none of these commands affect the DMA.
Reading Status
These two commands allow the CPU to read DMA status:
READ STATUS BYTE
Causes the next CPU read of the DMA to access the status byte. Every time
the status byte is to be read, the
written.
INITIATE READ SEQUENCE
Causes the next CPU read of the DMA to access the first status register
specified as readable by the read mask. Subsequent reads of the DMA,
which must complete the sequence of all designated readable registers, do
not require write commands. Reading of the sequence of registers must be
ENABLE DMA
command must be the last DMA command written before the return
command in the service routine before the
command, or WR3 bit 6 = 1, which is equivalent. Only
READ STATUS BYTE
RETI
Direct Memory Access
command must first be
instruction is
ENABLE
ENABLE