Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 95

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12. Contents of Counters After DMA Stops Due to Byte Match (Search or Transfer/
Search Operations)
UM008101-0601
Class
Notes
* Address can increment (+) or decrement (-) from the programmed starting address (As), which is the first
** Occurs only when the Ready line is still inactive just prior to the beginning of the last possible cycle in the
*** Search only has no destination. Simultaneous transfer/search cannot have both ports variable. This class of
Bus Control
address for transfer or search.
operation. For example, Ready is sampled inactive on the rising edge of CLK in the last cycle of the last read
operation.
operation is programmed as a DMA search only operation, with variable addresses assigned to the
programmed source port. What the DMA senses as the source port may be either the real source or destination,
as determined by external hardware. See the 'Applications' chapter.
:
Mode
Continuous
The DMA transfers and searches data by controlling the system buses in the
same way that the Z80 CPU controls them to perform read and write cycles.
Specifically, the DMA controls the following lines:
•
•
•
•
•
•
In addition, the DMA can also be programmed to watch a WAIT line
through its dual-purpose CE/WAIT pin.
Address Bus (16 bits)
Data Bus (8 bits)
IORQ
MREQ
RD
WR
Match Occurs
On This Byte
M
Bytes Transferred At Stop
If Transferring
M**
Byte Counter
M-1**
Source Port
Address Counter*
As±(M**
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N
Destination Port
Address Counter
***