Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 31

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Table 4. Channel Select Truth Table
CE
Chip Enable (input, active Low). A Low level on this pin enables the
CTC to accept control words, interrupt vectors, or time constant data
words from the Z80 data bus during an I/O Write cycle; or to transmit the
contents or the down-counter to the CPU during an I/O Read cycle. In
most applications this signal is decoded from the eight least-significant
bits of the address bus for any of the four I/O port addresses that are
mapped to the four Counter/Timer channels.
Clock(
System Clock (input). This single-phase clock is used by the CTC to
internally synchronize certain signals.
M1
Machine Cycle One Signal from CPU (input, active low). When M1 is
active and the RD signal is active, the CPU fetches an instruction from
memory. When M1 is active and the IORQ signal is active, the CPU
acknowledges an interrupt, alerting the CTC to place an interrupt vector on
the Z80 data bus if it has daisy-chain priority and one of its channels has
requested an interrupt.
Channel 0
Channel 2
Channel 3
Channel l
Φ
)
CS1
0
0
1
1
CS0
0
1
0
1
Counter/Timer Channels
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