Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 180
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
BUSREQ
Bus Release on Match
When the DMA is programmed to stop (release the bus) on match in Burst
or Continuous modes, a match causes BUSREQ to go inactive on the next
DMA operation, for example, at the end of the next read in search-only,
simultaneous transfer/searches, or at the end of the following write in
sequential transfer or transfer/searches (Figure 68).
Figure 68.
Because of the pipelining scheme, matches are determined while the next
DMA read or write is being performed. Table 12 lists the number of bytes
transferred in any class or mode.
The RDY line can go inactive after the matching operation begins without
affecting this bus-release timing. However, the time at which RDY goes
inactive can affect the number of bytes transferred, as described in Table 11
and Figure 32.
Bus Release on Not Ready
Burst mode, when RDY goes inactive, causes BUSREQ to go High on the
next rising edge of CLK after the completion of its current byte operation,
for example, at the end of the current read in search-only, simultaneous
transfer/search, or at the end of the following write in sequential transfer/
RDY
CLK
Active
Inactive
Bus Release on Match (Burst and Continuous Modes)
Read in
Byte n
Match Found
on Byte n
Byte n+1
Read in
and
Direct Memory Access
DMA
Inactive
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