Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 178

IC 6MHZ Z80 NMOS DART 40-DIP

Z0847006PSG

Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet

Specifications of Z0847006PSG

Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
BUSREQ
Note: RDY is detected as a level, not an edge
Figure 65.
Continuous mode is the only instance when a pulse on RDY allows the
DMA to become bus master.In this event, the DMA becomes bus master
but does not begin operations.
When the DMA detects a Low on BAI for two consecutive rising edges of
CLK, the DMA begins transferring data on the next rising edge of CLK.
In Byte mode, after each byte is transferred, the DMA waits until its BAI
line goes inactive before requesting the bus again on BUSREQ for the next
byte transfer. This feature allows a minimum of one CPU machine cycle to
occur between each byte transferred.
Bus Release Byte-at-a-Time
In Byte mode, BUSREQ is brought High on the rising edge of CLK prior to
the end of each read cycle (search-only) or write cycle (transfer and trans-
fer/search) as illustrated in Figure 66. This action occurs regardless of the
state of RDY. There is no possibility of confusion when a Z80 CPU is used
because the CPU cannot begin an operation until the following clock cycle.
Nor does this condition affect most other CPUs. The result of timing is one-
clock-cycle less time needed for a byte transfer.
RDY
CLK
BAI
Inactive
Active
Bus Request and Acceptance Timing
Inactive
DMA
Direct Memory Access
Active
DMA

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