Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 196

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIO ARCHITECTURE
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Overview
•
•
•
•
•
Figure 1 illustrates ablock diagram of the Z80 PIO. The internal structure of
the Z80 PIO consists of a Z80 CPU bus interface, internal control logic,
Port A I/O logic, Port B I/O logic, and interrupt control logic. The CPU bus
interface logic allows the PIO to interface directly to the Z80 CPU with no
other external logic. However, address decoders and/or line buffers may be
required for large systems. The internal control logic synchronizes the CPU
data bus to the peripheral device interfaces (Port A and Port B). The two
I/O ports (A and B) are virtually identical and are used to interface directly
to peripheral devices.
Figure 2 depicts the Port I/O logic is composed of 6 registers with hand-
shake control logic. The registers include: an 8-bit data input register, an
8-bit data output register, a 2-bit mode control register, an 8-bit mask
register, an 8-bit input/output select register, and a 2-bit mask control
register.
Four modes of port operation with interrupt-controlled handshake:
–
–
–
–
Daisy-chain priority interrupt logic, allowing automatic interrupt
vectoring without external logic
Eight outputs capable of driving darlington transistors
Fully TTL-compatible inputs and outputs
Single 5V supply and single-phase clock required
Byte Output
Byte Input
Byte Bidirectional Bus (available on Port A only)
Bit Control Mode
Parallel Input/Output