Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 132

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Read Registers
Enable DMA (87)
This command allows the DMA to request the system bus and proceed with
its operation if all other functional conditions are met, for example, if the
Ready line is active or the FORCE READY condition is present. This
command, and bit 6 of WR3, are the only control bytes that do not disable the
DMA. All other control bytes written to the DMA automatically disable the
DMA. Therefore, the
command after writing or reading any other bytes to or from the DMA.
This command enables the DMA’s bus request logic. It does not affect
interrupt logic and it does not reset any functions or latches. This bus-
request-enabling function is duplicated in bit 6 of WR3.
In an interrupt service routine, the ENABLE DMA command must be the
last command to the DMA before the CPU executes its return-from-
interrupt instruction.
Disable DMA (83)
This command prevents the DMA from requesting the bus. It is used to stop
DMA action for external reasons, such as a pending power-out, and in the
special case of reinitializing the status byte after a stop on end-of-block or a
stop on byte match (see the
Process Read registers by first writing a command to the DMA, then by
reading either immediately or later. Accomplish CPU reads by addressing
the DMA as an I/O device using input instructions (such as INIR for the
Z80 CPU).
Commands written to the DMA can be either of the following:
ENABLE DMA
REINITIALIZE STATUS BYTE
command is always required as the last
Direct Memory Access
command).