Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 282

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

262
Table 9. SDLC Transmit Mode
UM008101-0601
Function
Initialize WR0
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Register Information loaded:
WR0
WR2
WR0
WR3
WR0
In all modes, characters are sent with the least-significant bits first. This
requires right justification of data to be transmitted when the word length is
less than eight bits. If the word length is five bits or less, use the special
technique described in
Because the number of bits/character can be changed on-the-fly, the data
field can be filled with any number of bits. When used in conjunction with
the Receiver Residue codes, the Z80 SIO can receive a message that has a
variable I-field and retransmit it exactly as received with no previous infor-
mation about the character structure of the I-field (if any). A change in the
number of bits does not affect the character being shifted out. Characters
are sent with the number of bits programmed at the time that the character
is loaded from the transmit buffer to the transmitter.
If the External/Status Interrupt Enable is set, transmitter conditions, such as
“starting to send CRC characters,” “starting to send flag characters,” and CTS
changing state, cause interrupts, having a unique vector if Status Affects
Vector is set. All interrupts can be disabled for operation in a polled mode.
Table 9 describes the typical program steps that implement the half-duplex
SDLC Transmit mode.
Typical Program Steps
Channel Reset
Pointer 2
Interrupt Vector
Pointer 3
Auto Enables
Pointer 4, Reset External/status
Interrupts
“Write Register 5” on page
Comments
Reset SIO
Channel B only
Transmitter sends data only after CTS is
detected
289.
Serial Input/Output