Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 127

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Enable Interrupts (AB)
See the preceding description of DISABLE INTERRUPTS. A Z80 CPU
environment uses this command at power-up to enable the interrupt logic at
the beginning (the DMA comes up with this logic disabled). It is not
needed, however, to enable subsequent interrupts because this function is
provided for by the CPU’s fetching and the DMA’s decoding of the RETI
instruction. The only exception is when the DISABLE INTERRUPTS
command is used; the ENABLE INTERRUPTS command must also be
used to begin DMA operations again.
Any conditions selected to cause an interrupt are latched in the DMA even
when interrupts are disabled. They can then cause a later interrupt after
interrupts are reenabled.
The ENABLE INTERRUPTS command must not be written until after the
DMA has been configured and the REINITIALIZE STATUS BYTE
command has been written. This command has the same effect as writing a
1 to bit 5 of WR3.
Reset and Disable Interrupts (A3)
This command is useful in CPU environments such as the 8080 and 8085
where there is an interrupt acknowledge function but no RETI instruction,
as in the Z80 CPU. This command accomplishes four functions:
•
•
•
•
In the non-Z80 environment just described, it would be used as follows:
after the DMA interrupt is received and acknowledged, the interrupt
vector is sent to the CPU, which branches to the service routine. Near the
Resets the Interrupt Under Service (IUS) latch
Resets the Interrupt Pending (IP) latch
Unforces an internal FORCE READY condition
Disables further interrupts by the DMA (same as the DISABLE
INTERRUPTS command)
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N