Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 53

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
DMA Data Transfers
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Both transfer and response times on most CPUs are often too slow. While
transfer speed can be quite high with the Z80 and Z8000 CPUs, the
response time can be too long in interrupt-driven transfer situations.
A DMA controller (DMAC) performs direct data transfers between the
source and destination without going through the CPU, and without the
instruction fetches required by the CPU. It performs all of the steps illus-
trated in Figure 15 through hardware.
for example, in a memory-to-I/O transfer, the starting address in memory
and the length of the block to be transferred are written to the DMA by the
CPU before to the transfer. The DMAC begins transferring data when the
CPU enables the DMAC and the Ready line I/O of the device becomes
active. In most cases, the CPU is idle during a DMA transfer. When the
transfer is complete, the DMAC signals the CPU and releases control.
The I/O device interrupts the CPU and the block transfer instruction
is executed in the CPU interrupt service routine. This method has a
response time of at least 5 to 10 µs, even in 4 MHz Z80A and
Z8000 devices.
The CPU begins executing the device service routine before the I/O
device is ready, and a flag bit is constantly polled by the CPU. When
the flag bit indicates that the device is ready, the CPU jumps to the
block transfer instruction. This method sometimes produces a response
time of less than 5 µs, but it uses the entire capability of the CPU.
The CPU begins executing the block transfer instruction in an interrupt
service routine before the I/O device is actually ready. The I/O device
idles the CPU with the Wait line just after the Read and Chip-Select
lines become active. When the I/O device is ready, it releases the wait
line and the transfer is completed. This method gives the best response
time (250 ns in a 4 MHz Z80A or Z8000 CPU) but ties up the bus.
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
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