Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 208

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Loading The Interrupt Vector
In addition to the automatic power-on reset, the PIO can be reset by
applying an M1 signal without the presence of a RD or IORQ signal. If no
RD or IORQ is detected during M1, the PIO enters the reset state immedi-
ately after the M1 signal goes inactive. This reset allows a single external
gate to generate a reset without a power-down sequence. The 40-pin pack-
aging requires this routine.
When the PIO enters the internal reset state, it is held there until the PIO
receives a control word from the CPU.
The PIO is designed to operate with the Z80 CPU using the Mode 2 inter-
rupt response. This mode requires that an interrupt vector be supplied by
the interrupting device. This vector is used by the CPU to form the address
for the interrupt service routine of that port. This vector is placed on the
Z80 data bus during an interrupt acknowledge cycle by the highest priority
device requesting service at that time. (Refer to the Z80 CPU User’s
Manual Section for details on how an interrupt is serviced by the CPU).
The interrupt vector is loaded to the PIO by writing a control word to the
appropriate PIO port using the following format:
D0 functions as a flag bit, which when Low, loads V7 through V1 to the
vector register. At interrupt acknowledge, the vector of the interrupting port
appears on the Z80 data bus exactly as illustrated in the diagram above.
D7
V7
V6
D6
Signifies this Control Word
is an Interrupt Vector
D5
V5
V4
D4
D3
V3
D2
V2
D1
V1
D0
0
Parallel Input/Output