Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 201

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Φ
System Clock (input). The Z80 PIO uses the standard Z80 system clock to
synchronize certain signals internally. This is a single phase clock.
M1
Machine Cycle One Signal from CPU (input, active Low). This signal
from the CPU is used as a sync pulse to control several internal PIO opera-
tions. When M1 is active and the RD signal is active, the Z80 CPU is
fetching an instruction from memory. Conversely, when M1 is active and
IORQ is active, the CPU is acknowledging an interrupt. In addition, the M1
signal has two other functions within the Z80 PIO.
1. M1 synchronizes the PIO interrupt logic.
2. When M1 occurs without an active RD or IORQ signal, the PIO logic
enters a reset state.
IORQ
Input/Output Request from Z80 CPU (input, active Low). The IORQ
signal is used in conjunction with the B/ A Select, C/D Select, CE, and
RD signals to transfer commands and data between the Z80 CPU and the
Z80 PIO. When CE, RD, and IORQ are active, the port addressed by B/A
transfers data to the CPU (a read operation). Conversely, when CE and
IORQ are active but RD is not active, then the port addressed by B/A is
written to from the CPU with either data or control information as speci-
fied by the C/D Select signal. Also, if IORQ and M1 are active simulta-
neously, the CPU is acknowledging an interrupt and the interrupting port
automatically places its interrupt vector on the CPU data bus if it is the
highest priority device requesting an interrupt.
RD
Read Cycle Status from the Z80 CPU (input, active Low). If RD is active,
a MEMORY READ or I/O READ operation is in progress. The RD signal
is used with B/A Select, C/D Select, CE, and IORQ signals to transfer data
from the Z80 PIO to the Z80 CPU.
UM008101-0601
Parallel Input/Output