Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 328

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

308
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Daisy Chain Interrupt Nesting
D7–D0
The Tipple time of the interrupt daisy-chain, both the High-to-Low and
the Low-to-High transitions, limits the number of devices that can be
placed in the daisy-chain. Ripple time can be improved with carry-
lookahead, or by extending the interrupt acknowledge cycle.
Figure 131. Return from Interrupt Cycle Timing
Figure 132 illustrates the daisy-chain configuration of interrupt circuits and
their interaction with nested interrupts, which is an interrupt that is inter-
rupted by another with a higher priority.
Each box in the illustration can be a separate external Z80 peripheral circuit
with a user-defined order of interrupt priorities. However, a similar daisy-
chain structure also exists inside the Z80 SIO, which has six interrupt levels
with a fixed order of priorities.
The situation illustrated in Figure 132 occurs when the transmitter of
Channel B interrupts and is granted service. While this interrupt is being
serviced, it is interrupted by a higher priority interrupt from Channel A. The
second interrupt is serviced and, upon completion, a RETI instruction is
IEO
M1
RD
IEI
Φ
T
1
T
2
ED
T
3
T
4
T
1
T
2
4D
T
3
T
4
Serial Input/Output
T
1