Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 280

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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has been completely sent, the Transmit Buffer Empty status bit is set and an
interrupt is generated to indicate to the CPU that another message can
begin. This interrupt occurs because CRC is sent and the flag is loaded. If
no more messages are to be sent, the program can terminate transmission
by resetting RTS, disabling the transmitter.
In the SDLC mode, reset the Transmit Underrun/EOM status bit immedi-
ately after the first character is sent to the Z80 SIO. When the Transmit
Underrun is detected, this ensures that the transmission time is filled by
CRC characters, giving the CPU enough time to issue the Send Abort
command. This procedure also stops the flags from going on the line
prematurely and eliminates the possibility of the receiver accepting the
frame as valid data. For example, the data pattern, immediately preceding
the automatic flag insertion, could match the CRC checker, thereby giving a
false CRC check result. The External/Status interrupt is generated when-
ever the Transmit Underrun/EOM bit is set as a result of the Transmit
Underrun condition.
The transmit underrun logic provides additional protection from premature
flag insertion if the proper response is given to the Z80 SIO by the CPU
interrupt service routine. The following example illustrates this point:
1. The Z80 SIO interrupts with the Transmit Buffer Empty status bit set.
2. The CPU does not respond in a timely manner, which causes a
3. The Z80 SIO starts sending CRC characters (two bytes).
4. The CPU eventually satisfies the Transmit Buffer Empty interrupt
5. The Z80 SIO sets the External/Status interrupt with the Transmit
6. The CPU recognizes the Transmit Underrun/EOM status and
Transmit Underrun condition.
with a data character that follows the CRC character being
transmitted.
Underrun/EOM status bit set
determines from its internal program status that the interrupt is not
“end of message”.
Serial Input/Output