Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 36

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CTC PROGRAMMING
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Overview
Timing may be initialized automatically or with a triggering edge at the
channel’s Timer Trigger (CLK/TRG) input. This timing is determined by
programming bit 3 of the channel control word. If bit 3 is reset?, the timer
automatically begins operation at the start of the CPU cycle following the I/
O Write machine cycle that loads the time constant data word to the
channel.
If bit 3 is set, the timer begins operation on the second succeeding rising
edge of Φ after the Timer Trigger edge following the loading of the time
constant data word.
If no time constant word is to follow, the timer begins operation on the
second succeeding rising edge of Φ after the Timer Trigger edge and
following the control word write cycle. Bit 4 of the channel control word is
pre programmed to select whether the Timer Trigger is sensitive to a rising
or falling edge. There is no setup requirement between the active edge of
the Timer Trigger and the next rising edge of Φ.
If the Timer Trigger edge occurs closer than a specified minimum setup
time to the rising edge of Φ, the down-counter does not begin decrementing
until the following rising edge of Φ. If bit 7 in the channel control word is
set, the zero-count condition in the down-counter causes a pulse at the
channel’s Time Out pin, and initiates an interrupt request sequence. (For
more details, see “CTC Interrupt Servicing” on page 27).
To begin counting or timing operations, a Channel Control Word and Time
Constant Data Word are written to the appropriate channel by the CPU.
These words are stored in the Channel Control or Time Constant registers
of each channel. If a channel has been programmed to enable interrupts, an
interrupt vector is written to the appropriate register in the CTC. Because of
Counter/Timer Channels