Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 168

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Control Overhead
User Supplied
Continuous Mode
Continuous Mode monopolizes the bus until the end-of-block or byte
match is reached, regardless of the state of the Ready line. While
achieving the fastest transfer speeds, this mode is employed when no
time-critical functions are dependent upon the CPU or when the data
blocks are relatively short.
Byte mode is used for most applications. When considering the use of
Burst or Continuous modes, the following must be known:
•
•
•
The DMA can be forced off the bus in either Byte or Burst mode.
Figure 58 illustrates how an external gate is used to remove the RDY-
input state from the DMA. Forcing the DMA to stop in the middle of a
transfer cannot be used when the DMA is operating in Continuous mode.
Only a power-down or normal termination with end-of-block or byte
match can make the DMA release the bus.
Figure 58.
The CPU becomes less efficient when the DMA’s software must be
initialized or updated. As Table 15 illustrates, thirty-five control bytes are
required to initialize a fully functioning DMA. In addition, using the
Interrupt mode requires servicing by the CPU, which demands writing
additional control bytes to the DMA.
Maximum block length
Maximum DMA transfer rate (see Table 8)
Maximum time Ready line remains active
RDY
FORCE.OFF.BUS
DMA Bus-Master Gate (Byte or Burst Modes Only)
To DMA
Direct Memory Access